1. Field of the Invention
This invention relates to charge coupled device (CCD) technology, and more particularly, to semiconductor apparatus for providing respective output signals indicative of the sequential transfer of minority carrier packets from a CCD shift register.
2. Description of the Prior Art
A new class of monolithic semiconductor apparatus adapted for storing and sequentially transferring electronic signals representing information in the form of packets of excess minority carriers localized in artificially induced potential wells has been disclosed by W. S. Boyle and G. S. Smith, in an article entitled "Charge Coupled Semiconductor Devices," B.S.T.J. April, 1970, pages 587-593, inclusive. Such apparatus comprises a metal-insulator-semiconductor (MIS) structure wherein a plurality of metal electrodes are disposed in a row over the insulator (dielectric) which in turn overlies and is contiguous with the surface of a semiconductor body. Sequential application of voltages to the metal electrodes induces potential wells adjacent the surface of the semiconductor body in which packets of excess minority carriers can be stored and between which these packets can be transferred. To insure predictable directionality of charge packet transfer, the transfer potential well must be asymmetrical at least during the transfer operation. As disclosed in the Boyle-Smith disclosure, at least three phase clock pulses are required to provide the requisite asymmetry for a uniform dielectric thickness under the gate electrodes and a homogeneous semiconductor.
A two-phase clock CCD system is disclosed in U.S. Pat. No. 3,651,349 issued to Dawon Kahng and Edward H. Nicollian. Charge transfer is accomplished in this configuration by the use of overlapping gate electrodes and/or non-uniform dielectric thicknesses under the gate electrodes so that an appropriately asymmetrical potential well is always formed whenever a voltage is applied to any gate electrode.
Charge coupled devices have also been noted to be particularly adapted to the fabrication of an imaging array where for example a parallel readout of the array is first made to an adjacent shift register with the readout of the shift register then being accomplished serially. Such apparatus is shown in the article entitled "Charge-Coupled Imaging Devices: Experimental Results" published by G. F. Amelio, et al., and appearing in the IEEE Transactions on Electron Devices, November, 1971, at pages 992-996, inclusive.
A charge sensing circuit is also disclosed by the prior art. Such apparatus is disclosed in U.S. Pat. No. 3,623,132, issued to Robert D. Green, and discloses a first field effect transistor being turned "on" during a first phase recurring interval for charging a first capacitor at the gate electrode of an output field effect transistor. During a second phase recurring interval, a second field effect transistor is turned "on" for coupling the first capacitor to a second capacitor at the output of a charge coupled circuit. The voltage on the first capacitor causes an inversion or depletion under the fixed plate of the second capacitor. If the charge coupled circuit is charged, that is it has minority carriers, an inversion region is formed under the fixed plate and electrically connects the second capacitor to the charge coupled circuit. Normally the charge coupled circuit is charged when a binary logic 1 is provided at the input to the circuit. If the inversion layer is formed, the voltage on the first capacitor is substantially reduced and the output transistor is turned "off." If the charge coupled circuit is not charged as when a logic 0 is provided at the input of the charge coupled circuit, the semiconductor substrate beneath the second capacitor plate is only depleted. The voltage on the first capacitor is reduced only slightly, and the output field effect transistor remains "on." The logic state of the charge coupled circuit is sensed by determining whether or not the output field effect transistor remains "on" or is turned "off."